Employment Options

MEO WEBINAR:  Job Application TipsSave the date: June 13th @ 3PM ET

Senior FPGA Research Engineer – (MEO 759)

Kimberly Bounds

Location: Northern VA near Washington DC
Schedule: Tues through Thurs on-site
Must be a US citizen
Pay Range: $130,000 – $160,000

My client, a technology research organization, is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead research in algorithm development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems.  Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across the company, publish results in top tier conferences, and contribute to or lead proposals.

Qualifications

  • MS or Bachelors and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
  • Strong software development (C++/Java/Python) and hardware design (VHDL/Verilog/System Verilog) experience.
  • 3-5 years of experience using Xilinx, Intel, or Lattice FPGA implementation tools.
  • Qualified candidates for this position must be willing and eligible to apply for a Top Secret clearance. Eligibility for this clearance requires U.S. citizenship. Current SECRET clearance or higher is a plus.

Preferred Job Qualifications:

  • Experience using or contributing to open-source EDA tools such as Torc, RapidWright, ABC, VPR, VTR, RapidSmith, nextpnr, prjXray.
  • Demonstrable experience in one of the following topics: FPGA CAD tool algorithms (synthesis, partitioning, mapping, placing, routing), design automation, or hardware trust, assurance, and security.
  • Experience with software revision control systems such as Git, Mercurial, SVN and CI/CD development workflows.

Minimum Education

  • Bachelor’s degree with 7 years of experience.
  • MS or Bachelors and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
  • Strong software development (C++/Java/Python) and hardware design (VHDL/Verilog/System Verilog) experience.
  • 3-5 years of experience using Xilinx, Intel, or Lattice FPGA implementation tools.
  • Qualified candidates for this position must be willing and eligible to apply for a Top Secret clearance. Eligibility for this clearance requires U.S. citizenship.
  • Current SECRET clearance or higher is a plus.

Why is This a Great Opportunity

Very interesting work with national security implications. I can’t imagine this kind of work being done anywhere else…. modifying design tools used in ASIC and FPGA design.

If you are interested in this position, please send your resume to [email protected]

To apply for this job please visit myemploymentoptions.com.



Tags: